1. Field of the Invention
The present invention relates to a method for calculating delay time, program for calculating delay time and device for calculating delay time needed in a circuit design. More particularly, the present invention relates to a method for calculating delay time, program for calculating delay time and device for calculating delay time needed in a circuit design of a semiconductor device miniaturized and highly integrated.
2. Description of the Related Art
Patent Document 1 shown below has been conventionally disclosed. Procedures for calculating delay time in a desired circuit use condition of each circuit element constituting a semiconductor device based on data stored in a coefficient table 150 are shown in the Patent Document 1. Herein, the circuit use condition is the process condition, use temperature and power supply voltage of the semiconductor device.
In the delay time calculating processing shown in FIG. 5, in step 210, based on various data stored in data files 110 to 130, the standard delay time tpd0 of the semiconductor device in a standard use condition is calculated. In step 220, delay time ratio coefficient DMAG100 in a desired circuit use condition is read out from delay time ratio coefficient table 150, and the delay time tpd is calculated as tpd=tpd0×DMAG100 in step 240.
Herein, the delay time ratio coefficient DMAG100 is a value of the ratio of the standard delay time tpd0 and delay time calculated according to the circuit use condition. A delay time in the circuit use condition is calculated by multiplying the delay time ratio coefficient DMAG100 to the standard delay time tpd0. The delay time is generally expressed as a linear function of a monotone increase to the circuit use condition such as a process condition, a use temperature and a power supply voltage.
The timing verification needs verification in the circuit use condition operating in the minimum delay time and the maximum delay time as a boundary condition, and the delay time ratio coefficient DMAG100 is the linear function of the monotone increase to the circuit use condition. Thereby, the minimum value/maximum value of the delay time ratio coefficient DMAG100 at the time of calculating the minimum/maximum delay time is a value in the condition of both ends in the circuit use condition. That is, the minimum delay time is calculated by delay time ratio coefficient in the fastest process condition, lowest use temperature and the maximum power supply voltage, and the maximum delay time is calculated by delay time ratio coefficient in the latest process condition, maximum use temperature and the minimum power supply voltage. The timing verification is performed based on the delay time ratio coefficient in the condition of both ends in the circuit use condition.
The above prior art reference is as follows.    Patent Document 1: Japanese Published Unexamined Patent Application H11-3366